This invention relates to a data transfer unit which is incorporated in a data processing unit.
In a data processing unit such as a processor, an efficient data transfer leads to better performance of the processor as a whole.
In a case where the data processing unit transfers a large amount of data, when a CPU (general-purpose processor) performs the data transfer, another process which is supposed to be executed by the CPU is delayed, which leads to a problem that the performance of the entire system is deteriorated.
In order to solve the above-mentioned problem, a current data processing unit generally employs a data transfer processor called direct memory access controller (DMAC), which is used to transfer data in place of the CPU (see, for example, JP 06-149749 A, JP 06-282515 A, and JP 09-330288 A). Accordingly, the CPU is merely required to set a data transfer start command to the DMAC, and can perform another process while the DMAC is performing data transfer.
According to the above-mentioned method, the CPU is required to set the data transfer start command to the DMAC when the data transfer is necessary. Further, there also arises a need to monitor whether the DMAC is in operation or not.
To set the data transfer start command for each data transfer as described above may not appear as overhead as long as a transfer data length is long, but it may appear as a large overhead when the transfer data length is short, which hinders improvements in performance. Also, there is a growing demand for an optimization technology in which a compiler is employed to automatically insert a data transfer instruction, which otherwise requires difficult programming, to thereby avoid the troublesome programming work. However, in a case where the above-mentioned optimizing compiler has analyzed, based on a certain computation, that a plurality of data transfers are necessary, the CPU drives the DMAC at each of the data transfers, which still leads to a large overhead, making it difficult to efficiently create the data transfer instructions by the compiler.
As regards a method for reducing the number of times to set the data transfer start command by the CPU, there has been proposed a method called command chain. According to the command chain, instead of giving a data transfer start instruction through the CPU each time the data transfer is performed, all the data transfer instructions are set as a list on a storage device in advance and the CPU instructs the DMAC to perform data transfer according to each one of the data transfer instructions from the top of the list, to thereby cause the DMAC to sequentially read the transfer instructions on the storage device and perform data transfer.
According to this method, the CPU only executes a start of the first data transfer, and the DMAC performs the data transfer after the first data transfer by starting the commands. Accordingly, the CPU is required to set the data transfer start command only once. Therefore, the CPU can allocate time, which conventionally would have been needed to set the data transfer command, to another processing. Further, with the data transfer function of the DMAC, which is highly autonomous as described above, it is possible to efficiently execute data transfer, which has been analyzed to be necessary by the compiler, during execution.